1. Field of the Invention
The present invention relates to cache memory, and more particularly, the invention relates to a memory unit and a memory module applicable to a cache memory.
2. Description of the Related Art
Cache memory is located functionally between a processor and a main memory. The cache memory is generally faster but smaller than the main memory. The cache memory decreases memory access time by storing copies of portions of the contents of main memory. When a local process performs certain “cachable” operations requiring memory access, the cache memory is checked first to determine if it contains a copy of the information to be accessed. If the cache memory contains a copy of the information to be accessed, the processor performs the operation using the cache memory without accessing main memory. A cache “hit” occurs when the information to be accessed by a cachable operation is stored in the cache memory, and a cache “miss” occurs when the information is not.
A main memory address consists of two fields (not shown) The higher order bits are called the tag field, and the remaining lower order bits are called the index field. As shown in FIG. 1, the cache memory 10 uses a tag memory, separate from data memory, to store the tag fields of the addresses of the main memory contents presently stored. When the processor performs memory access, the index field of the address addresses the tag memory. The output data from the tag memory is then compared bit by bit with the tag field of the main memory address. If the two fields are identical, a hit has occurred, and the corresponding data is supplied to the processor. If the fields are not identical, it is a miss, and main memory must be accessed.
If the contents of the tag memory become corrupted, memory accesses that should miss actually hit. This results in incorrect data supplied to the processor, a dangerous situation. It is common to use a signal parity bit over each byte in the tag memory, whereas, if a bad parity is detected when the tag memory is read, a miss condition is forced.
Conventionally, all information in tag memory is stored by SRAM cells, each having structure as shown in FIG. 2a. During flushing operation, the tag memory is invalidated entry by entry and requires sequential circuits such that the performance of the cache system is affected.
Another conventional method stores the parity bit (control field) of the tag memory using memory banks with new cell structures as shown in FIGS. 2b and 2c, and conventional SRAM cells as shown in FIG. 2a store information of the address field, attribute field and so on. Virtual ground/power terminals (VG/VP) of all cells for the parity bit in the tag memory are connected together to be forced ground/power voltage for flush operations. Although this method requires fewer additional control logic circuits, it requires asynchronous circuits and is poorly compatible with timing analysis. Further, this method has no tolerance for that there cannot be any signal glitch or system noise between the virtual power/ground terminals and the memory units, with which the data stored in the memory units may be unreliable.